One embodiment of the invention relates to a nonvolatile semiconductor memory and particularly to a nonvolatile semiconductor memory having memory cell transistors stacked for providing a large memory capacity.
A NAND nonvolatile semiconductor memory has a configuration wherein transistors each containing a charge storage layer in a gate insulating film, for example, memory cell transistors of a stacked gate structure having a floating gate electrode layer or memory cell transistors (MONOS structure or SONOS structure) each with an insulating film (ONO structure) implemented as a stacked structure of silicon oxide film/silicon nitride film/silicon oxide film as a gate insulating film are connected in series as memory cells and both ends are sandwiched between selection gate transistors of usual MOS transistors.
If the selection gate transistor is a transistor implemented as a stacked structure of the same structure as the memory cell transistor, the possibility that electrons or holes may be stored in the charge storage layer of the selection gate transistor because of a voltage stress in a read state is not nil although it is not intended that write or erase is executed for the selection gate transistor. In this case, if the selection gate transistor is an n-channel MOS transistor, it is not turned on as the threshold value becomes high by storing electrons in the charge storage layer or it is not turned off as the threshold value becomes low by storing holes in the charge storage layer, and these situations cause a problem of hindering selectivity. Thus, the selection gate transistor needs a manufacturing process separate from the memory cell transistor.
If the memory cell transistor has an ONO structure, a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed on a silicon semiconductor substrate or a silicon oxide film and a silicon nitride film are formed and then in the portion which will become a selection gate transistor region, once formed insulating film is peeled off and then a silicon oxide film is formed by oxidation for forming the selection gate transistor as a usual MOS transistor.
If the memory cell transistor has a floating gate structure, it is desirable that the selection gate transistor and the memory cell transistor should be of the same structure in working on gates containing lithography. Therefore, although the gate electrode of the lower layer is not separated for each selection gate transistor, the selection gate transistor also becomes a two-layer structure. However, it becomes a floating gate structure as it is and thus it is necessary to provide a contact portion of a two-layer gate made up of a floating gate electrode layer and a control gate electrode layer at a cell array end or in a cell array.
As described above, the manufacturing process is complicated in the presence of the selection gate transistor, and a space accompanying separation creation of a gate insulating film is required between the selection gate transistor and the memory cell transistor, and a space to connect one gate electrode layer with an other gate electrode layer becomes necessary, resulting in an increase in the memory cell size or the memory cell array region.
An example of applying a memory cell transistor of a thin film transistor (TFT) having a charge storage dielectric layer of an ONO structure placed in a NAND string connected in series to three-dimensional flash memory is already disclosed. (For example, refer to USP Laid-Open No. 2004/0124466 and A. J. Walker, et al., “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” 2003 Symposium on VLSI Technology Digest of Technical Papers, June 2003).) Likewise, three-dimensional mask programmable ROM and its peripheral circuit configuration are also already disclosed. (For example, refer to USP Laid-Open No. 2004/0155302.)
Three-dimensional PROM having a stack structure wherein eight layers of diode/antifuse memory cells are placed in a longitudinal direction is already disclosed. (For example, refer to M. Johnson, et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Antifuse Memory Cells,” IEEE J. Solid-State Circuits, Vol. 38, No. 11, pp. 1920-1928, November 2003).) Further, NAND flash memory based on incremental step pulse programming (ISPP) scheme for making it possible to decrease page program current by self-boosting program suppression voltage and accomplishing high-speed read throughput with an interleaved data path is already disclosed. (For example, refer to K-D. Sung, et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” 1995 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 128-129, 15-17 Feb. 1995).)